CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

Effect of gate length in InAs/AlSb HEMTs biased for low power or high gain

Malin Borg (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik) ; Eric Lefebvre (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik) ; Mikael Malmkvist (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik) ; Ludovic Desplanque ; Xavier Wallart ; Yannick Roelens ; Gilles Dambrine ; Alain Cappy ; Sylvain Bollaert ; Jan Grahn (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik)
Solid-State Electronics (0038-1101). Vol. 52 (2008), 5, p. 775-781.
[Artikel, refereegranskad vetenskaplig]

The effect of gate-length variation on DC and RF performance of InAs/AlSb HEMTs, biased for low DC power consumption or high gain, is reported. Simultaneously fabricated devices, with gate lengths between 225 nm and 335 nm, have been compared. DC measurements revealed higher output conductance gds and slightly increased impact ionization with reduced gate length. When reducing the gate length from 335 nm to 225 nm, the DC power consumption was reduced by approximately 80% at an fT of 120 GHz. Furthermore, a 225 nm gate-length HEMT biased for high gain exhibited an extrinsic fT of 165 GHz and an extrinsic fmax of 115 GHz, at a DC power consumption of 100 mW/mm. When biased for low DC power consumption of 20 mW/mm the same HEMT exhibited an extrinsic fT and fmax of 120 GHz and 110 GHz, respectively.

Nyckelord: HEMT, AlSb, InAs, gate length



Denna post skapades 2009-10-09. Senast ändrad 2016-08-16.
CPL Pubid: 99924

 

Läs direkt!


Länk till annan sajt (kan kräva inloggning)


Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik

Ämnesområden

Elektronik

Chalmers infrastruktur