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Zero-Value Caches: Cancelling Loads that Return Zero.

Mafijul Islam (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Stenström (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
2009 18th International Conference on Parallel Architectures and Compilation Techniques, PACT 2009; Raleigh, NC; United States; 12 September 2009 through 16 September 2009 (1089-795X). p. 237-245 . (2009)
[Konferensbidrag, refereegranskat]

The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads. loads accessing memory locations that contain the value.zero. to improve performance and energy dissipation. Our study shows that such loads comprise as many as 18% of the total number of dynamic loads. We show that a significant fraction of zero loads ends up on the critical memory-access path in out-oforder cores. We propose a non-speculative microarchitectural technique. Zero-Value Cache (ZVC). to capitalize on zero loads and explore critical design options of such caches. We show that with modest investment, we can obtain speedups up to 78% and reduce the overall energy dissipation by up to 39%. Most importantly, zero-value caches never cause performance loss.



Denna post skapades 2009-05-29. Senast ändrad 2016-08-18.
CPL Pubid: 94515

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Information Technology

Chalmers infrastruktur

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