CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

Influence of Electron Charge States in Nanoelectronic Building Blocks

Johan Piscator (Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik)
Göteborg : Chalmers University of Technology, 2009. ISBN: 978-91-7385-281-4.- 66 s.

The continued efforts to improve performance and decrease size of semiconductor logic devices are facing serious challenges. In order to further develop one of the most important nanoelectronic building blocks, the metal-oxide-semiconductor field-effect-transistor (MOSFET), several major problems have to be solved. This thesis deals with the influence of charge states on two specific issues related to the continued scaling of the MOSFET, the increasing source/drain resistance and the need for a high-k oxide in the MOS gate stack. A silicon nanowire with Schottky source/drain contacts is fabricated on a silicon-on-insulator substrate using electron-beam lithography. It is shown analytically and experimentally how the introduction of positive charge in the oxide surrounding the wire lowers the effective Schottky barrier due to the added dipole potentials. By using the backside as a gate and measuring the current through the wire as a function of temperature, effective barrier heights of the source and drain contacts can be extracted. The Al/HfO$_{2}$/Si MOS structure has been studied in detail using electrical characterization methods primarily based on capacitance and conductance measurements. In particular, the properties of charge traps at the HfO$_{2}$/Si interface have been studied and it is shown that they resemble the traps found for SiO$_{2}$/Si interfaces, pointing to the existence of $P_{b}$ centers also for high-k oxides. It has also been found that an interlayer exists between the HfO$_{2}$ and Si regions. This transition region is an SiO$_{x}$-like material with a graded composition which can explain the occurrence of $P_{b}$-like traps at the interface. Furthermore the classical conductance method for investigations of oxide-semiconductor interfaces is extended in order to more accurately determine the energy dependence of capture cross sections. For traps at the interface, it is found that two different capture mechanisms dominate in different energy intervals: phonon cascade capture close to the conduction band and multi-phonon capture for deeper states.

Nyckelord: Schottky contacts, silicon nanowire, silicon on insulator (SOI), Schottky barrier lowering, high-k, MOS, interface states, conductance method, CV, TSC.

Denna post skapades 2009-05-14. Senast ändrad 2013-09-25.
CPL Pubid: 94093


Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Fysikalisk elektronik (2007-2010)


Den kondenserade materiens fysik
Defekter och diffusion

Chalmers infrastruktur


Datum: 2009-06-12
Tid: 10:00
Lokal: Kollektorn (A423), MC2, Kemivägen 9, Chalmers University of Technology
Opponent: Prof. Enrico Sangiorgi, University of Bologna, Italy

Ingår i serie

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie 2962

Technical report MC2 - Department of Microtechnology and Nanoscience, Chalmers University of Technology 144