CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

Zero-Value Caches: Cancelling Loads that Return Zero

Mafijul Islam (Institutionen för data- och informationsteknik (Chalmers)) ; Sally A McKee (Institutionen för data- och informationsteknik (Chalmers)) ; Per Stenström (Institutionen för data- och informationsteknik (Chalmers))
Göteborg : Chalmers University of Technology, 2009. - 18 s.
[Rapport]

The speed gap between processor and memory continues to limit performance. To address this problem, we explore the potential of eliminating Zero Loads — loads accessing memory locations that contain the value “zero” — to improve performance and energy dissipation. Our study shows that such loads comprise as many as 18% of the total number of dynamic loads. We show that a significant fraction of zero loads ends up on the critical memory-access path in out-of-order cores. We propose a non-speculative microarchitectural technique — Zero-Value Cache (ZVC) — to capitalize on zero loads and explore critical design options of such caches. We show that with modest investment (typically a 576-byte structure), we can obtain speedups up to 78% and reduce the overall energy dissipation up to 39%. Most importantly, zero-value caches never cause performance loss.

Nyckelord: Zero-Value Cache, Load Scheduling, Load Criticality, Frequent Value Locality, Zero Load



Denna post skapades 2009-04-15. Senast ändrad 2016-03-22.
CPL Pubid: 92517

 

Läs direkt!


Länk till annan sajt (kan kräva inloggning)


Institutioner (Chalmers)

Institutionen för data- och informationsteknik (Chalmers)

Ämnesområden

Datorteknik

Chalmers infrastruktur

Relaterade publikationer

Inkluderade delarbeten:


Zero Loads: Canceling Load Requests by Tracking Zero Values