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Single stage CMOS Power Amplifier at 23 GHz

Hossein Mashad Nemati (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik) ; Mattias Ferndahl (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik) ; Christian Fager (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik) ; Herbert Zirath (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik)
Abstarct and presentation in Workshop: RF Measurement Technology, for State of the Art Production and Design (2007)
[Konferensbidrag, övrigt]

A single stage CMOS power amplifier (PA) is designed and characterized. According to simulations, a power added efficiency (PAE) of 20% is achieved with 5 dB of gain and 12 dBm of output power at 23GHz. Differences between measurement and simulation are observed. A through analysis explaining these differences is presented. Measurements show a frequency shift to 18.9 GHz with 10dBm of output power, PAE equal to 5%, and a gain of 3.2 dB. The frequency shift is mainly related to the effect of RF-pads which are measured to be as a parallel capacitor with a value of 200 fF. The design was based on device model provided by the foundry which did not include extrinsic parasitic components especially the gate resistance which is the main reason for gain degradation.

Nyckelord: power amplifier, CMOS



Denna post skapades 2008-11-10. Senast ändrad 2015-12-17.
CPL Pubid: 77568

 

Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik

Ämnesområden

Elektroteknik och elektronik

Chalmers infrastruktur