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A VLSI Array Architecture for Artificial Neural Networks

Lars Bengtsson (Institutionen för datorteknik, Embedded and Networked Processors)
Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence, Cancun, 19-21 May 2003 p. 50-57. (2003)
[Konferensbidrag, refereegranskat]

A highly parallel array architecture for ANN algorithms is presented and evaluated. The array, consisting of PEs inter-connected as a 2D-grid, executes instructions according to the SIMD (Single Instruction Multiple Data) parallel computing model. The architecture is scalable, both in terms of problem size and when porting it to future down-scaled CMOS processes. As typical ANN examples, the feed-forward net with back-propagation training, and the Kohonen Self Organizing Feature Map are used. Performance metrics such as Connection-Updates-Per-Second (CUPS) and Connections-Per-Second (CPS) are derived based on test implementations. A VLSI test chip design is presented in order to show the feasibility of implementing the architecture.

Nyckelord: Artificial Neural Networks, Backpropagation, Self-Organizing-Feature-Maps, VLSI array architecture

Denna post skapades 2006-09-19. Senast ändrad 2013-02-20.
CPL Pubid: 7629


Institutioner (Chalmers)

Institutionen för datorteknik, Embedded and Networked Processors (2002-2004)


Information Technology

Chalmers infrastruktur