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**Harvard**

Islam, M. och Stenström, P. (2008) *Zero Loads: Canceling Load Requests by Tracking Zero Values*.

** BibTeX **

@conference{

Islam2008,

author={Islam, Mafijul and Stenström, Per},

title={Zero Loads: Canceling Load Requests by Tracking Zero Values},

booktitle={9th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '08, Held in Conjunction with the PACT 2008 Conference; Toronto, ON; Canada; 26 October 2008 through 26 October 2008},

pages={16-23},

abstract={The considerable gap between processor and DRAM speed and the power losses in the cache hierarchy calls for more efficient approaches. Broadly speaking, cache-hierarchy efficiency can be increased either by improving cache management or by reducing the number of load instructions that reach the cache hierarchy. We introduce the notion of zero loads to approach the latter. This paper explores the potential of tracking locations that contain the value 'zero'. Loads directed to such locations - termed Zero Loads - can be cancelled before they are issued in the cache hierarchy. We find that as many as 21% of the loads are Zero Loads and about one third of them are critical, i.e., ends up on the critical memory path for out-of-order cores. Motivated by this observation, we explore two innovative structures to capture Zero Loads by essentially book-keeping earlier visited blocks/locations that return 'zero'. These schemes are shown to be capable of improving performance and power/energy efficiency considerably.},

year={2008},

}

** RefWorks **

RT Conference Proceedings

SR Print

ID 74288

A1 Islam, Mafijul

A1 Stenström, Per

T1 Zero Loads: Canceling Load Requests by Tracking Zero Values

YR 2008

T2 9th MEDEA Workshop on MEmory Performance: DEaling with Applications, Systems and Architecture, MEDEA '08, Held in Conjunction with the PACT 2008 Conference; Toronto, ON; Canada; 26 October 2008 through 26 October 2008

SP 16

OP 23

AB The considerable gap between processor and DRAM speed and the power losses in the cache hierarchy calls for more efficient approaches. Broadly speaking, cache-hierarchy efficiency can be increased either by improving cache management or by reducing the number of load instructions that reach the cache hierarchy. We introduce the notion of zero loads to approach the latter. This paper explores the potential of tracking locations that contain the value 'zero'. Loads directed to such locations - termed Zero Loads - can be cancelled before they are issued in the cache hierarchy. We find that as many as 21% of the loads are Zero Loads and about one third of them are critical, i.e., ends up on the critical memory path for out-of-order cores. Motivated by this observation, we explore two innovative structures to capture Zero Loads by essentially book-keeping earlier visited blocks/locations that return 'zero'. These schemes are shown to be capable of improving performance and power/energy efficiency considerably.

LA eng

OL 30