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Cache Coherency Protocol Including Generic Transient States

Per Stenström (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
(2008)
[Patent]

In one embodiment, a cache comprises a cache memory and a cache control circuit coupled to the cache memory. The cache memory is configured to store a plurality of cache blocks and a plurality of cache states. Each of the plurality of cache states corresponds to a respective one of the plurality of cache blocks. The cache control circuit is configured to implement a cache coherency protocol that includes a plurality of stable states and a transient state The transient state may be used in response to any request from a local consumer if completing the request includes a change between the plurality of stable states and making the change includes transmitting at least a first communication to maintain coherency on an interconnect.



Denna post skapades 2008-08-03. Senast ändrad 2009-12-18.
CPL Pubid: 72636

 

Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Information Technology

Chalmers infrastruktur