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Gate Level Description of Synchronous Hardware and Automatic Verification Based on Theorem Proving

Per Bjesse (Institutionen för datavetenskap)
Göteborg : Chalmers University of Technology, 2001. ISBN: 91-7291-018-6.

Today's hardware development industry faces enormous problems. The primary reason for this is that the complexity of state-of-the-art hardware devices is growing faster than the capacity of the tools that are used to check that they are correct. This problematic situation is further aggravated by an increasing pressure to make the development time as short as possible. As a consequence, components under design are more likely to contain errors, while less time can be spent making sure that finished products are correct.

In this thesis, we contribute to improved hardware design methods in two ways.

First, we present Lava, a hardware description and verification platform that is embedded in the functional language Haskell. Lava uses the capabilities of the host language to express synchronous circuits in a mathematically precise way, and allows easy connection to external verification tools. Lava also uses the capabilities of Haskell to allow the designer to devise interconnection patterns, and to write parametrised circuit descriptions. We illustrate the power of Lava by describing and verifying hardware components for computing the Fast Fourier Transform (FFT).

Second, we present a number of techniques and case studies that demonstrate how automatic theorem proving can be used to prove correctness and find bugs in synchronous hardware. We show how verification can be done both at the level of complex arithmetic, and at the boolean level. In the case of the verification at the arithmetic level, we use Lava to construct special purpose proof strategies that interface with a first order logic theorem prover. In the case of the verification at the boolean level, we convert a number of standard finite state verification methods to use propositional logic theorem provers. The resulting converted methods are shown to give order of magnitude speedups compared to current state-of-the art verification techniques.

Denna post skapades 2006-08-25. Senast ändrad 2013-09-25.
CPL Pubid: 690


Institutioner (Chalmers)

Institutionen för datavetenskap (1993-2001)


Information Technology

Chalmers infrastruktur

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