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Evolutionary Optimisation of a Morphological Image Processor for Embedded Systems

Andreas K. Magnusson (Institutionen för tillämpad mekanik)
Göteborg : Chalmers University of Technology, 2008. ISBN: 978-91-7385-078-0.- 224 s.

The work presented in this thesis concerns the design, development and implementation of two digital components to be used, primarily, in autonomously operating embedded systems, such as mobile robots. The first component is an image coprocessor, for high-speed morphological image processing, and the second is a hardware-based genetic algorithm coprocessor, which provides evolutionary computation functionality for embedded applications. The morphological image coprocessor, the Clutter-II, has been optimised for efficiency of implementation, processing speed and system integration. The architecture employs a compact hardware structure for its implementation of the morphological neighbourhood transformations. The compact structure realises a significantly reduced hardware resource cost. The resources saved by the compact structure can be used to increase parallelism in image processing operations, thereby improving processing speed in a similarly significant manner. The design of the Clutter-II as a coprocessor enables easy-to-use and efficient access to its image processing capabilities from the host system processor and application software. High-speed input-output interfaces, with separated instruction and data buses, provide effective communication with system components external to the Clutter-II. A substantial part of the work presented in this thesis concerns the practical implementation of morphological filters for the Clutter-II, using the compact transformation structure. To derive efficient filter implementations, a genetic algorithm has been developed. The algorithm optimises the filter implementation by minimising the number of operations required for a particular filter. The experience gained from the work on the genetic algorithm inspired the development of the second component, the HERPUC. HERPUC is a hardware-based genetic algorithm processor, which employs a novel hardware implementation of the selection mechanism of the algorithm. This, in combination with a flexible form of recombination operator, has made the HERPUC an efficient hardware implementation of a genetic algorithm. Results indicate that the HERPUC is able to solve the set of test problems, to which it has been applied, using fewer fitness evaluations and a smaller population size, than previous hardware-based genetic algorithm implementations.

Nyckelord: morphological image processing, hardware-based genetic algorithm, embedded system, machine vision

Denna post skapades 2008-02-14. Senast ändrad 2013-09-25.
CPL Pubid: 68248


Institutioner (Chalmers)

Institutionen för tillämpad mekanik (1900-2017)



Chalmers infrastruktur


Datum: 2008-03-17
Tid: 10:00
Lokal: HA1
Opponent: Prof. Colin Reeves, Coventry University, UK

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