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Silicon device substrate and channel characteristics influenced by interface properties

Mikael Johansson (Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik)
Göteborg : Chalmers University of Technology, 2005. ISBN: 91-7291-682-6.- 90 s.

This thesis is divided in two parts, one dealing with the depleted Si/Si structure, which is a substrate behaving as a semi-insulating material intended for radio-frequency applications and the other concerning high-k gate dielectrics (dielectrics with high dielectric constant) as the replacement for silicon dioxide as MOS gate dielectric. High frequency applications of CMOS integrated circuits, to lower cost, achieve higher performance and richer functionality, depends partly on the possibility to decrease the substrate coupling between different parts of the circuit. The depleted Si/Si structure is a type of semi-insulating substrate that by fabrication technical efforts introduces a depleted layer between a silicon device film and the silicon bulk, with the intension to minimize substrate coupling and substrate losses. In contrast to the alternative approach of using standard Silicon-On-Insulator solutions the depleted structure will not confine the thermal dissipation. Characterization show that the depleted substrate is superior to standard silicon bulk material in the case of suppressing the crosstalk, and may have potential as a substrate for high frequency or mixed mode integration applications. The continuing scaling of the MOS transistor introduces new problems to overcome. One of the most prominent ones is the increased power dissipation and lowered reliability that results from the thinning of the gate dielectric layer. SiO2 has been the perfect gate oxide and has survived 30 years of scaling but may now have reached its limit. The high-k gate dielectrics may solve the leakage and reliability problem since it can be maid thicker and still achieve the needed result. However, there is still lot of work to be done to fully realize the replacement of SiO2, such as deposition and formation techniques as well as a deeper understanding of the high-k structure and interface behavior. In this work we contribute to the big picture of high-k gate dielectrics by characterizing different oxides and interfaces.

Nyckelord: semi-insulating, cross-talk, attenuation, interface, channel, hfo2, zro2, high-k, mos, traps

Public defence will be in english

Denna post skapades 2007-01-15. Senast ändrad 2013-09-25.
CPL Pubid: 6807


Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik (2003-2006)


Elektroteknik och elektronik

Chalmers infrastruktur


Datum: 2005-10-07
Tid: 09.30
Lokal: 09.30 Kollektorn, MC2, Chalmers
Opponent: Professor, Henryk Przewlocki, ITE Warszawa, Polen

Ingår i serie

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie 2364

Technical report MC2 - Department of Microtechnology and Nanoscience, Chalmers University of Technology 43