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Efficient Management of Speculative Data in Hardware Transactional Memory Systems

Mrida Mohammad Waliullah (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Stenström (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Göteborg : Chalmers University of Technology, 2007. - 13 s.
[Rapport]

Transactional memory systems promise to simplify parallel programming by avoiding deadlock, livelock, and serialization problems through optimistic, concurrent execution of code segments that potentially can have data conflicts with each other. Data conflict detection in proposed hardware transactional memory systems is done by associating a read bit with each cache block that is set when a block is speculatively read. However, since the set of blocks that have been speculatively read – the read set – has to be maintained until the transaction commits, one can often not replace a block that has been speculatively read. This leads to poor utilization of the private caches in a multi-core system. We propose a new scheme for managing the read set in hardware transactional memory systems. The novel insight is that unlike in proposed systems, where data in a block that is speculatively read is kept in cache, we note that only the address of that block is needed. As a result, there is an opportunity to reduce the space needed to keep track of speculatively read blocks by B/A, where B is the block size and A is the block address. Assuming that B is 32 bytes and A is 32 bits, there is an eightfold space saving due to this. This paper presents a novel design for leveraging this opportunity and evaluates a concept that uses a Bloom filter to hash the addresses of the read set into a structure. We find that the proposed scheme utilizes the private cache more efficiently and removes around 90% of the private cache overflows.



Denna post skapades 2007-12-14.
CPL Pubid: 63046