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Improving Execution Efficiency by Targeting Redundancy and Parallelism

Mafijul Islam (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Göteborg : Chalmers University of Technology, 2007.
[Licentiatavhandling]

Nyckelord: chip-multiprocessors, energy-efficiency, trivial computation, redundancy, instruction reuse, thread-level parallelism, thread-level speculation, performance, looptrip count, control speculation.


ISSN 1652-876X, Division of Computer Engineering



Denna post skapades 2007-09-21. Senast ändrad 2007-10-02.
CPL Pubid: 49329

 

Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Datorteknik

Chalmers infrastruktur

Relaterade publikationer

Inkluderade delarbeten:


Energy and Performance Tradeoffs between Instruction Reuse and Trivial Computations for Embedded Applications


Loop-Level Speculative Parallelism in Embedded Applications.


Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications


Examination

Datum: 2007-11-19
Tid: 10:00
Lokal: Room VK, Sven Hultins gata 6, Department of Civil and Environmental Engineering, Chalmers University of Technology
Opponent: Marcelo Cintra, School of Informatics, University of Edinburgh, UK

Ingår i serie

Technical report L - Department of Computer Science and Engineering, Chalmers University of Technology and Göteborg University 43L