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Current Probing Methodology for Static Power Extraction in Sub-90nm CMOS Circuits

Minh Quang Do (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Mindaugas Drazdziulis (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Göteborg : Chalmers University of Technology, 2007. ISBN: 2007-07.- 11 s.
[Rapport]

Static power dissipation is steadily increasing, calling for the full attention of circuit designers. As a result of scaling, static currents are flowing in a very complex manner through digital circuits. For example, static currents flow through the interface between CMOS gates, which is in contrast to when only subthreshold leakage was considered. It follows that the methodology for probing circuits for current measurements during simulation has become complex.We explain how to account, in circuit simulation, for static currents in CMOS circuits in general, and show the detailed probing strategy for a number of central gates: a NAND gate, an SRAM cell and the full adder.

Nyckelord: VLSI, CMOS, Deep Submicron, Power Estimation, SRAM Power Modeling



Denna post skapades 2007-05-11. Senast ändrad 2016-09-14.
CPL Pubid: 41553