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Capturing Process-Voltage-Temperature (PVT) Variations in Architectural Static Power Modeling for SRAM Arrays

Minh Quang Do (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Mindaugas Drazdziulis (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Göteborg : Chalmers University of Technology, 2007. - 9 s.

We propose a modeling methodology, including power models, that captures the dependence of leakage power on temperature and supply voltage variations for accurate architectural-level power estimation of physically partitioned and un-partitioned SRAMarrays. A simulation -based modeling approach is used for temperature-aware leakage power estimation, while a physically-based analytical approach is used for modeling the leakage dependence of memory cells on supply voltage. By using the new power models, it is, for example, possible to preserve our previously reported power estimation accuracy of 96% also in the presence of temperature and voltage variations.

Nyckelord: VLSI, CMOS, Deep Submicron, Power Estimation, SRAM Power Modeling

Denna post skapades 2007-05-11. Senast ändrad 2016-09-14.
CPL Pubid: 41547