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Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays

Minh Quang Do (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Mindaugas Drazdziulis (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Lars Bengtsson (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
8th International Symposium on Quality Electronic Design (ISQED’07) p. 185 - 191. (2007)
[Konferensbidrag, refereegranskat]

We propose a methodology and power models for an accurate high-level power estimation of physically partitioned and power-gated SRAM arrays. The models offer accurate estimation of both dynamic and leakage power, including the power dissipation due to emerging leakage mechanisms such as gate oxide tunneling, for partitioned arrays that deploy data-retaining sleep techniques for leakage reduction. Using the proposed methodology, dynamic, leakage and total power of partitioned SRAM arrays can be estimated with a 97% accuracy in comparison to the power obtained by running full circuit-level simulations.

Nyckelord: VLSI, CMOS, Deep Submicron, Power Estimation, SRAM Power Modeling


IEEE Catalog Number E2853



Denna post skapades 2007-04-03. Senast ändrad 2016-09-14.
CPL Pubid: 40335

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Datorteknik

Chalmers infrastruktur

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