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Modelling of High Power SOI Vertical DMOS Transistors and Flip-chip Packages

Kuntjoro Pinardi (Institutionen för mikroelektronik)
Göteborg : Chalmers University of Technology, 2003. ISBN: 91-7291-274-X.- 52 s.

Part I: Vertical DMOS Transistors

System level integration is a major trend in the electronic industry at the moment. For automotive applications in particular it is desirable to integrate CMOS logic circuits and different types of power devices. One of the methods to separate these devices from each other is by having a Silicon-on-Insulator (SOI) material providing dielectric isolation between high and low voltage parts. An important question is related to the performance of these dielectrically isolated devices. High power vertical DMOS transistors (VDMOSFETs) on SOI are demonstrated with a CMOS compatible fabrication process. A large number of defects are created in the structure if the trench formation is performed prior to the device fabrication. The defect generation has been reduced signicantly by moving the trench formation towards the end of fabrication steps. In this way the trenches are not exposed to high temperatures.

Our measurements of the fabricated SOI VDMOSFETs in the static region are in good agreement with the expected impact of the self-heating simulations on the saturation behaviour. Looking into details the carrier dynamics during the Unclamped Inductive Switching test can easily reveal the potential of having the parasitic bipolar transistors turned on. Furthermore high-temperature measurements point out that the parasitic BJT effect is activated. Switching simulations show that the substrate and oxide capacitors provide a second path for the current to flow during the discharging of the inductor. It can happen that the maximum current through the SOI device is separated in time from the maximum voltage across the device, thereby reducing the maximum power.

Part II: Finite Element Calculations of Flip-chip Joints

Flip-chip joining using anisotropically conductive adhesive (ACA) has become a very attractive technique for electronics packaging. In this work, the strain development during the thermal cycling test of ip-chip joining with different bump heights was studied. The effect of bump height is signicant in the interface between the bumps and the pads. Our calculations show that there is practically no effect of the bump height on the strain variation in the bumps and in the pads.

Nyckelord: SOI, vertical DMOS, integration, UIS, self-heating, Unclamped Inductive Switching, Flip-chip, Conductive Adhesive, ACA

Denna post skapades 2006-08-28. Senast ändrad 2013-09-25.
CPL Pubid: 389


Institutioner (Chalmers)

Institutionen för mikroelektronik (1995-2003)


Elektroteknik och elektronik

Chalmers infrastruktur

Ingår i serie

Technical report - School of Electrical Engineering, Chalmers University of Technology, Göteborg, Sweden 440

Doktorsavhandlingar vid Chalmers tekniska högskola. Ny serie 1956