CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

A Surface Potential Model for Predicting Substrate Noise Coupling in Integrated Circuits

Simon Kristiansson (Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik) ; Fredrik Ingvarson (Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik) ; Shiva P. Kagganti (Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik) ; Kjell Jeppson (Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik)
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, CICC; Orlando, FL; United States; 3 October 2004 through 6 October 2004 (08865930). p. 497-500. (2004)
[Konferensbidrag, refereegranskat]

In integrated circuits, it must be verified that noise injected and transmitted through the substrate does not degrade the performance of sensitive circuitry present on the chip. In this paper, we present a simple analytic substrate model for evaluating substrate noise coupling. The model handles an arbitrary number of aggressor and victim devices as well as biased and floating chip backside. The model has been validated by measurements on test structures manufactured in a 0.35 /spl mu/m CMOS process, and it is shown that the model gives an accurate description of the substrate noise coupling. For example, the noise suppressing properties of guard rings have been evaluated.

Nyckelord: CMOS integrated circuits, coupled circuits, integrated circuit modelling, integrated circuit noise, interference suppression, surface potential, 0.35 micron, CMOS, IC substrate noise coupling, aggressor devices, biased chip backside, floating chip backside, guard rings noise suppressing properties, substrate injected noise, substrate transmitted noise, surface potential model, victim devices



Denna post skapades 2007-01-15. Senast ändrad 2017-01-27.
CPL Pubid: 2944

 

Läs direkt!


Länk till annan sajt (kan kräva inloggning)


Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Fasta tillståndets elektronik (2003-2006)

Ämnesområden

Elektroteknik och elektronik

Chalmers infrastruktur

Relaterade publikationer

Denna publikation ingår i:


Substrate Noise Coupling Modelling in Mixed-Signal Integrated Circuits: A Surface Potential Approach