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Using Lava and Wired for Design Exploration

Emil Axelsson (Institutionen för data- och informationsteknik, Datavetenskap (Chalmers)) ; Koen Claessen (Institutionen för data- och informationsteknik, Datavetenskap (Chalmers)) ; Mary Sheeran (Institutionen för data- och informationsteknik, Datavetenskap (Chalmers))
Proceedings of the sixth international workshop on designing correct circuits, March, Vienna, Mary Sheeran and Tom Melham (editors) (2006)
[Artikel, övrig vetenskaplig]

Lava has been used successfully in structural circuit description and layout generation for FPGAs. It has been demonstrated that Lava is suitable for describing so-called "clever" or adaptive circuits -- circuits whose structure adapts to various properties of their contexts. This can be incorporated quite naturally into the descriptions due to the fact that Lava is embedded in the powerful functional programming language Haskell. The rising problems associated with chip design in the deep sub-micron (DSM) era calls for new methods that are able to account for low-level effects already in higher-level descriptions. In particular, interconnect wires need to be modeled in order to get reliable estimates of non-functional properties, such as delay and power consumption. We are working on a system -- Wired -- which aims to bring the ideas from Lava down to lower levels. What distinguishes Wired from other layout-aware languages is the fact that we are modeling Wires explicitly, and that we can have adaptive descriptions whose structure adapts to accurate estimates of, for example, signal delays in their context. Here we demonstrate a flow for design exploration using parallel prefix circuits \cite{PP} as example. The descriptions start of in Lava, and are then transformed, surprisingly smoothly, into corresponding Wired descriptions. We demonstrate several classic parallel prefix structures as well as a family of new ones. Wired has the capability of performing a number of different signal analyses on the descriptions. We can, for example, analyse for signal flow direction and delay. Our most advanced delay model uses Elmore approximation to appropriately take account of fanout and load capacitance. We will use the available analysis methods to compare the different parallel prefix structures. Hopefully, we will also be able to demonstrate examples of delay-adaptive circuits in time for the DCC workshop.



Denna post skapades 2007-01-16.
CPL Pubid: 25624

 

Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datavetenskap (Chalmers)

Ämnesområden

Datavetenskap (datalogi)

Chalmers infrastruktur

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