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PHOENIX: Efficient computation in memory

Mats Rimborg (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Pedro Trancoso (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Gunnar Carlstedt (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
ACM International Conference Proceeding Series. 2017 International Symposium on Memory Systems, MEMSYS 2017; Washington; United States; 2-5 October 2017 Vol. Part F131197 (2017), p. 15-25.
[Konferensbidrag, refereegranskat]

Parallelism is inherent in most problems but due to current programming models and architectures which have evolved from a sequential paradigm, the parallelism exploited is restricted. We believe that the most efficient parallel execution is achieved when applications are represented as graphs of operations and data, which can then be mapped for execution on a modular and scalable processing-in-memory architecture. In this paper, we present PHOENIX, a general-purpose architecture composed of many Processing Elements (PEs) with memory storage and efficient computational logic units interconnected with a mesh network-on-chip. A preliminary design of PHOENIX shows it is possible to include 10,000 PEs with a storage capacity of 0.6GByte on a 1.5cm2 chip using 14nm technology. PHOENIX may achieve 6TFLOPS with a power consumption of up to 42W, which results in a peak energy efficiency of at least 143GFLOPS/W. A simple estimate shows that for a 4K FFT, PHOENIX achieves 117GFLOPS/W which is more than double of what is achieved by state-of-the-art systems.

Nyckelord: Energy-efficient; High-performance computing (HPC); Parallel architectures; Processing-in-memory (PIM)



Denna post skapades 2017-12-15. Senast ändrad 2017-12-22.
CPL Pubid: 253798

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Data- och informationsvetenskap

Chalmers infrastruktur