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Leveraging data promotion for low power D-NUCA caches

Alessandro Bardine ; Manuel Comparetti ; Pierfrancesco Foglia ; Giacomo Gabrielli ; Cosimo Antonio Prete ; Per Stenström (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008; Parma; Italy; 3 September 2008 through 5 September 2008 (2008)
[Konferensbidrag, refereegranskat]

D-NUCA caches are cache memories that, thanks to banked organization, broadcast search and promotion/demotion mechanism, are able to tolerate the increasing wire delay effects introduced by technology scaling. As a consequence, they will outperform conventional caches (UCA, Uniform Cache Architectures) in future generation cores. Due to the promotion/demotion mechanism, we observed that the distribution of hits across the ways of a D-NUCA cache varies across applications as well as across different execution phases within a single application. In this work, we show how such a behavior can be leveraged to improve the D-NUCA power efficiency as well as to decrease its access latency. In particular, we propose: 1) A new microarchitectural technique to reduce the static power consumption of a D-NUCA cache by dynamically adapting the number of active (i.e. powered-on) ways to the need of the running application; our evaluation shows that a strong reduction of the average number of active ways (37.1%) is achievable, without significantly affecting the IPC (-2.83%), leading to a resultant reduction of the Energy Delay Product (EDP) of 30.9%. 2) A strategy to estimate the characteristic parameters of the proposed technique. 3) An evaluation of the effectiveness of the proposed technique in the multicore environment.



Denna post skapades 2017-11-30.
CPL Pubid: 253454

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Data- och informationsvetenskap

Chalmers infrastruktur