CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

Micro-architectural power estimation and optimization

Babak Hidaji (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Mohamad Reza Andalibizadeh (Institutionen för data- och informationsteknik (Chalmers)) ; Salar Alipour (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
2009 IEEE International Conference on Electro/Information Technology, EIT 2009; Windsor, ON; Canada; 7 June 2009 through 9 June 2009 p. 446-450. (2009)
[Konferensbidrag, refereegranskat]

Today power optimization is an important field of research due to the increasing need for less power consumption, dramatic decrease of circuit's MTBF on high temperature and cooling difficulties. It is investigated that only 30% improvement in battery performance will be obtained in five years [1]. This paper is an overview on Power estimation and optimization researches and the overall flow of presenting the information is based on the reference [17]. We review the architectural template and the methods to provide model for power consumption of different types of components. Some common optimization techniques including clock-gating, exploiting the common case of the design and managing voltage are being reviewed.

Denna post skapades 2017-11-13.
CPL Pubid: 253091


Läs direkt!

Länk till annan sajt (kan kräva inloggning)