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Heterogeneous- and NUMA-aware scheduling for many-core architectures

P. Petrides ; Pedro Trancoso (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
SYSTOR 2017 - Proceedings of the 10th ACM International Systems and Storage Conference p. Article no. 2. (2017)
[Konferensbidrag, refereegranskat]

© 2017 ACM. As the number of cores increases in a single chip processor, several challenges arise: wire delays, contention for out-ofchip accesses, and core heterogeneity. In order to address these issues and the applications demands, future large-scale many-core processors are expected to be organized as a collection of NUMA clusters of heterogeneous cores. In this work we propose a scheduler that takes into account the non-uniform memory latency, the heterogeneity of the cores, and the contention to the memory controller to find the best matching core for the application's memory and compute requirements. Scheduler decisions are based on an on-line classification process that determines applications requirements either as memory- or compute-bound. We evaluate our proposed scheduler on the 48-core Intel SCC using applications from SPEC CPU2006 benchmark suite. Our results show that even when all cores are busy, migrating processes to cores that match better the requirements of applications results in overall performance improvement. In particular we observed a reduction of the execution time from 15% to 36% compared to a random static scheduling policy.



Denna post skapades 2017-07-18.
CPL Pubid: 250737

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Datorteknik

Chalmers infrastruktur