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Direct extraction of MOS transistor model parameters

Peter R. Karlsson (Institutionen för fasta tillståndets elektronik) ; Kjell Jeppson (Institutionen för fasta tillståndets elektronik ; Institutionen för mikroelektronik och nanovetenskap)
Analog Integrated Circuits and Signal Processing (0925-1030). Vol. 5 (1994), 3, p. 199–212.
[Artikel, refereegranskad vetenskaplig]

The direct extraction method of MOS transistor parameters is summarized and results from its application to the first Norchip 1µm CMOS process run are presented. Two different transistor models (SPICE level 3 and BSIM) have been used, and both models are found to be useful at least down to 1µm devices: typical average relative errors between measured and calculated currents are in the 2-9% range. Two methods of calculating the difference between drawn and effective geometries have been compared. The influence of the source/drain series resistance is also discussed.

Nyckelord: Parameter extraction, MOSFET model parameters

Denna post skapades 2017-01-29.
CPL Pubid: 247819


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Institutioner (Chalmers)

Institutionen för fasta tillståndets elektronik (1985-1998)
Institutionen för mikroelektronik och nanovetenskap (1900-2003)


Elektroteknik och elektronik

Chalmers infrastruktur