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Test chip and data considerations for MOS parameter extraction

Peter R. Karlsson (Institutionen för fasta tillståndets elektronik) ; Kjell Jeppson (Institutionen för fasta tillståndets elektronik ; Institutionen för mikroelektronik och nanovetenskap)
Proceedings of the IEEE International Conference on Microelectronic Test Structures ICMTS Vol. 1997 (1997), 17-20 March 1997,
[Konferensbidrag, refereegranskat]

This paper presents an investigation of principles for test chip design and data point selection for MOS parameter extraction methods using a low number of data points. Variations in extracted parameter values for different combinations and numbers of data points are studied experimentally. The influences on the standard deviations of V/sub T/, /spl beta/, /spl theta/, R/sub S/, /spl Delta/W and /spl Delta/L of different data point selections and device combinations are studied using synthetic data with multiplicative noise.

Nyckelord: Parameter extraction, Data mining, MOSFETs, Noise measurement, Geometry, Voltage, Circuit noise, Electronic equipment testing, Chip scale packaging, Semiconductor device measurement

Denna post skapades 2017-01-29.
CPL Pubid: 247818


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Institutioner (Chalmers)

Institutionen för fasta tillståndets elektronik (1985-1998)
Institutionen för mikroelektronik och nanovetenskap (1900-2003)


Elektroteknik och elektronik

Chalmers infrastruktur