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A parallel hierarchical design rule checker

Nils Hedenstierna (Institutionen för fasta tillståndets elektronik) ; Kjell Jeppson (Institutionen för fasta tillståndets elektronik ; Institutionen för mikroelektronik och nanovetenskap)
[3rd] European Conference on Design Automation Vol. 1992 (1992), p. 142-146.
[Konferensbidrag, refereegranskat]

The halo algorithm, a novel and efficient algorithm for hierarchical design-rule checking (DRC) has been modified for parallel processing. Like the sequential halo algorithm, the parallel version identifies repeated subcell interactions and checks them only once thereby improving performance substantially. Inverse layout trees are used to handle interacting primitives hierarchically. The algorithm has been implemented on workstations connected by a local area network and on a shared memory multicomputer.

Nyckelord: Data mining, Solid state circuits, Parallel processing, Workstations, Local area networks, Concurrent computing, Very large scale integration, Wires, Testing, Data structures

Denna post skapades 2017-01-28.
CPL Pubid: 247807


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Institutioner (Chalmers)

Institutionen för fasta tillståndets elektronik (1985-1998)
Institutionen för mikroelektronik och nanovetenskap (1900-2003)


Elektroteknik och elektronik

Chalmers infrastruktur