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The halo algorithm-an algorithm for hierarchical design of rule checking of VLSI circuits

Nils Hedenstierna (Institutionen för fasta tillståndets elektronik) ; Kjell Jeppson (Institutionen för fasta tillståndets elektronik ; Institutionen för mikroelektronik och nanovetenskap)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (0278-0070). Vol. 12 (1993), 2, p. 265 - 272.
[Artikel, refereegranskad vetenskaplig]

The halo algorithm, a new and efficient hierarchical algorithm for corner-based design rule checking, is presented. The basic idea is to check each cell in its context by first identifying all elements that interact with the cell, thereby completely eliminating the rechecks of the traditional hierarchical methods. Identical interactions, repeated at several instances of a cell, are identified and checked as one interaction. The concept of the inverse layout tree is introduced to handle the interacting primitives. No restrictions are enforced on the hierarchical structure of the layout, and error messages are placed in the cells where the errors should be corrected. Performance is exemplified using several test-circuits. It is shown that the halo algorithm offers a five to twentyfold speed increase when the hierarchical circuit description is verified instead of a flattened description.

Nyckelord: Algorithm design and analysis, Very large scale integration, Transistors, Error correction, Circuit testing, Wire, Solid state circuits

Denna post skapades 2017-01-28.
CPL Pubid: 247806


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Institutioner (Chalmers)

Institutionen för fasta tillståndets elektronik (1985-1998)
Institutionen för mikroelektronik och nanovetenskap (1900-2003)


Elektroteknik och elektronik

Chalmers infrastruktur