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Formal definitions of edge-based geometric design rules

Nils Hedenstierna (Institutionen för fasta tillståndets elektronik) ; Sven Christensson (Institutionen för fasta tillståndets elektronik) ; Kjell Jeppson (Institutionen för fasta tillståndets elektronik ; Institutionen för mikroelektronik och nanovetenskap)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (0278-0070). Vol. 12 (1993), 1, p. 59-69.
[Artikel, refereegranskad vetenskaplig]

A structured method for geometric design rule definitions is presented in terms of edge-based constraints. Using this approach, intralayer design rules such as width and spacing of single layers, and interlayer design rules such as clearance, margin, extension, and overlap of two different layers can be specified in terms of two high-level design rule macros only. The tedious and complicated task of specifying detailed design rules in the technology file is thereby eliminated and placed by a simple macro rule file giving a much better overview of the design rules. Efficient rule compilers have been developed to expand these macro descriptions of the design rules onto basic checks for Magic and for corner-based design rule checking. As an example, the MOSIS scalable CMOS design rule set can be described in terms of the two design rule macros only. More complicated design rules, such as conditional and conjunctive design rules, are also discussed.

Nyckelord: Process design, Design methodology, Integrated circuit layout, Fabrication, Integrated circuit yield, Production, Very large scale integration, Computer aided manufacturing, Design automation, Manufacturing processes



Denna post skapades 2017-01-28.
CPL Pubid: 247802

 

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Institutioner (Chalmers)

Institutionen för fasta tillståndets elektronik (1985-1998)
Institutionen för mikroelektronik och nanovetenskap (1900-2003)

Ämnesområden

Data- och informationsvetenskap
Elektroteknik och elektronik

Chalmers infrastruktur