CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

Negative bias stress of MOS devices at high electric fields and degradation of MNOS devices

Kjell Jeppson (Institutionen för mikroelektronik och nanovetenskap) ; Christer Svensson
Journal of Applied Physics (0021-8979). Vol. 48 (1977), 5, p. 2004-2014.
[Artikel, refereegranskad vetenskaplig]

One of the most important degradation effects observed in MNOS memory transistors is a negative shift of the threshold window. This negative shift is caused by a strong increase of the density of Si‐SiO2 surface traps. This effect has been proposed to be caused by the same effect that is observed in MOS devices subjected to negative‐bias stress (NBS). In this paper, a detailed study of the increase of the number of surface traps in MOS structures after NBS at temperatures (25–125°C) and fields (400–700 MV/m) comparable to those used in MNOS devices is presented. Two different behaviors are observed. At low fields the surface‐trap density increases as t^1/4 and at high fields it increases linearly with the stress time t. The low‐field behavior is temperature and field dependent and the zero‐field activation energy is determined to be 0.3 eV. The high‐field behavior is strongly field dependent but independent of temperature. A physical model is proposed to explain the surface‐trap growth as being diffusion controlled at low fields and tunneling limited at high fields. A comparison with MNOS degradation is made and it was found to be related to the t^1/4 behavior mentioned above.

Nyckelord: Field-effect transistors, MOSFET, Negative Bias Stress, NBTI

Denna post skapades 2017-01-27. Senast ändrad 2017-07-10.
CPL Pubid: 247791


Läs direkt!

Lokal fulltext (fritt tillgänglig)

Länk till annan sajt (kan kräva inloggning)

Institutioner (Chalmers)

Institutionen för mikroelektronik och nanovetenskap (1900-2003)


Elektroteknik och elektronik

Chalmers infrastruktur