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Low-Power 400-Gbps Soft-Decision LDPC FEC for Optical Transport Networks

Kevin Cushon (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Peter Andrekson (Institutionen för mikroteknologi och nanovetenskap, Fotonik)
Journal of Lightwave Technology (0733-8724). Vol. 34 (2016), 18, p. 4304-4311.
[Artikel, refereegranskad vetenskaplig]

We present forward error correction systems based on soft-decision low-density parity check (LDPC) codes for applications in 100–400-Gbps optical transport networks. These systems are based on the low-complexity “adaptive degeneration” decoding algorithm, which we introduce in this paper, along with randomly-structured LDPC codes with block lengths from 30 000 to 60 000 bits and overhead (OH) from 6.7% to 33%. We also construct a 3600-bit prototype LDPC code with 20% overhead, and experimentally show that it has no error floor above a bit error rate (BER) of 10−15 using a field-programmable gate array (FPGA)-based hardware emulator. The projected net coding gain at a BER of 10−15 ranges from 9.6 dB at 6.7% OH to 11.2 dB at 33% OH. We also present application-specific integrated circuit synthesis results for these decoders in 28 nm fully depleted silicon on insulator technology, which show that they are capable of 400-Gbps operation with energy consumption of under 3 pJ per information bit.

Nyckelord: Application-specific integrated circuit (ASIC) synthesis; forward error correction (FEC); low-density parity-check (LDPC) codes; low power

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Denna post skapades 2016-09-15. Senast ändrad 2017-09-28.
CPL Pubid: 241825


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