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Resilient chip multiprocessors with mixed-grained reconfigurability

Ioannis Sourdis (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Danish Anis Khan (Institutionen för data- och informationsteknik (Chalmers)) ; Alirad Malek (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Stavros Tzilis (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Georgios Smaragdos ; Christos Strydis
IEEE Micro (0272-1732). Vol. 36 (2016), 1, p. 35.
[Artikel, refereegranskad vetenskaplig]

This article presents a chip multiprocessor (CMP) design that mixes coarse- and fine-grained reconfigurability to increase core availability of safety-critical embedded systems in the presence of hard errors. The authors conducted a comprehensive design-space exploration to identify the granularity mixes that maximize CMP fault tolerance and minimize performance and energy overheads. The authors added fine-grained reconfigurable logic to a coarse-grained sparing approach. Their resulting design can tolerate 3 times more hard errors than core redundancy and 1.5 times more than any other purely coarse-grained solution.

Nyckelord: Adaptable architectures; Availability; CMP; Microarchitecture implementation considerations; Multicore; Pipeline implementation; Reconfigurable hardware; Reliability; Serviceability; Single-chip multiprocessor

Denna post skapades 2016-07-04. Senast ändrad 2016-09-14.
CPL Pubid: 238881


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Denna publikation är ett resultat av följande projekt:

on-Demand System Reliability (DESYRE) (EC/FP7/287611)