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Another Trip to the Wall: How Much Will Stacked DRAM Benefit HPC?

M. Radulovic ; D. Zivanovic ; D. Ruiz ; B. R. De Supinski ; Sally A McKee (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; P. Radojkovíc ; E. Ayguad
ACM International Conference Proceeding Series - Proceedings of the 1st International Symposium on Memory Systems, MEMSYS 2015, Washington, United States, 14-15 August 2015 Vol. 05-08-October-2015 (2015), p. 31-36.
[Konferensbidrag, refereegranskat]

First defined two decades ago, the memory wall remains a fundamental limitation to system performance. Recent innovations in 3D-stacking technology enable DRAM devices with much higher bandwidths than traditional DIMMs. The first such products will soon hit the market, and some of the publicity claims that they will break through the memory wall. Here we summarize our analysis and expectations of how such 3D-stacked DRAMs will affect the memory wall for a set of representative HPC applications. We conclude that although 3D-stacked DRAM is a major technological innovation, it cannot eliminate the memory wall.

Nyckelord: Bandwidth, Dram, High bandwidth memory (hbm), Hpc, Hybrid memory cube (hmc), Latency, Memory wall

Denna post skapades 2016-03-23. Senast ändrad 2016-09-12.
CPL Pubid: 233623


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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)


Data- och informationsvetenskap

Chalmers infrastruktur