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Practical Way Halting by Speculatively Accessing Halt Tags

Daniel Moreau (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Alen Bardizbanyan (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Magnus Själander (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; David Whalley ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
19th Design, Automation and Test in Europe Conference and Exhibition, DATE 2016, Dresden, Germany, 14-18 March 2016 (1530-1591). p. 1375-1380. (2016)
[Konferensbidrag, refereegranskat]

Conventional set-associative data cache accesses waste energy since tag and data arrays of several ways are simultaneously accessed to sustain pipeline speed. Different access techniques to avoid activating all cache ways have been previously proposed in an effort to reduce energy usage. However, a problem that many of these access techniques have in common is that they need to access different cache memory portions in a sequential manner, which is difficult to support with standard synchronous SRAM memory. We propose the speculative halt-tag access (SHA) approach, which accesses low-order tag bits, i.e., the halt tag, in the address generation stage instead of the SRAM access stage to eliminate accesses to cache ways that cannot possibly contain the data. The key feature of our SHA approach is that it determines which tag and data arrays need to be accessed early enough for conventional SRAMs to be used. We evaluate the SHA approach using a 65-nm processor implementation running MiBench benchmarks and find that it on average reduces data access energy by 25.6%.

Article number 7459523

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Denna post skapades 2016-03-14. Senast ändrad 2016-10-14.
CPL Pubid: 233173


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