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Mixed-signal implementation of differential decoding using binary message passing algorithms

G. Cowan ; Kevin Cushon (Institutionen för mikroteknologi och nanovetenskap, Fotonik) ; W. Gross
Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors (1063-6862). Vol. 2015-September (2015), p. 116-119.
[Konferensbidrag, refereegranskat]

© 2015 IEEE. This paper presents the mixed-signal circuit implementation of reduced complexity algorithms for decoding low-density parity check (LDPC) codes. Based on modified differential decoding using binary message passing (MDD-BMP), binary addition using discrete-time digital circuits is replaced by continuous-time analog-current summation. Potential degradation due to the mismatch between current sources, P/N strength mismatch and inverter-threshold mismatch is considered in behavioural simulation and shown to be tolerable. Area estimates suggest a reduction from 0.27 mm2 to 0.11 mm2 for the FG(273, 191) code. Finally, transistor level simulation of the FG(273, 191) code using TSMC 65 nm technology shows an efficiency of 0.56 pJ/bit.

Nyckelord: analog circuits, binary messages, energy efficient, iterative decoding, LDPC, VLSI

Denna post skapades 2016-02-10. Senast ändrad 2016-08-23.
CPL Pubid: 231887


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Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Fotonik


Elektroteknik och elektronik

Chalmers infrastruktur