CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

On Maximum Current Estimation in CMOS Digital Circuits

Dainius Ciuplys (Institutionen för datorteknik, Integrerade elektroniksystem) ; Per Larsson-Edefors (Institutionen för datorteknik, Integrerade elektroniksystem)
International Conference on VLSI Design, Mumbai, INDIA. JAN 05-09, 2004 p. 658-661. (2004)
[Konferensbidrag, refereegranskat]

We show the importance of accounting for supply currents on the quiet power terminal when analyzing impact of peak currents on power distribution network. The quiet power terminal is defined for any signal transition in the CMOS inverter as the contact point opposite to the (dis)charging terminal. We investigate the current dynamics on these supposedly quiet contact points, and describe their dependencies on output load and input transition times. We furthermore propose triangular model representations for the quiet terminal current and its slope; the latter necessary to enable L (.) dI/dt prediction.

Denna post skapades 2006-09-12. Senast ändrad 2016-09-14.
CPL Pubid: 2307


Läs direkt!

Länk till annan sajt (kan kräva inloggning)

Institutioner (Chalmers)

Institutionen för datorteknik, Integrerade elektroniksystem (2002-2004)


Information Technology

Chalmers infrastruktur