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Glitch-Conscious Low-Power Design of Arithmetic Circuits

Henrik Eriksson (Institutionen för datorteknik, Integrerade elektroniksystem) ; Per Larsson-Edefors (Institutionen för datorteknik, Integrerade elektroniksystem)
2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004 (02714310). Vol. 2 (2004), p. II281-II284.
[Konferensbidrag, refereegranskat]

Glitches are common in arithmetic circuits, especially in large multipliers where they often represent the major part of transitions. With the aim to provide a judicious glitch-reduction strategy, we extract and study the relation between generated and propagated glitches for three different arithmetic blocks. We show that the number of propagated glitches is far bigger than those generated regardless of circuit type, supply voltage, and threshold voltage. In contrast to existing glitch-reduction strategies we propose to focus also on the glitch propagation mechanism. It is shown how the inverting property of adder cells can be harnessed to reduce propagation of glitches and thus the overall power dissipation.

Denna post skapades 2006-09-12. Senast ändrad 2016-09-14.
CPL Pubid: 2305


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Institutioner (Chalmers)

Institutionen för datorteknik, Integrerade elektroniksystem (2002-2004)


Information Technology

Chalmers infrastruktur