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Evaluation of Power Cut-Off Techniques in the Presence of Gate Leakage

Mindaugas Drazdziulis (Institutionen för datorteknik, Integrerade elektroniksystem) ; Per Larsson-Edefors (Institutionen för datorteknik, Integrerade elektroniksystem)
2004 IEEE International Symposium on Cirquits and Systems - Proceedings; Vancouver, BC; Canada; 23 May 2004 through 26 May 2004 (02714310 ). p. II745-II748. (2004)
[Konferensbidrag, refereegranskat]

We consider gate leakage next to subthreshold leakage currents in power-saving techniques for future CMOS circuits. Two recently introduced power cut-off techniques are analyzed and compared with respect to the total leakage current using Berkeley PTM. The results show that the efficiency of techniques having logic circuits alternately connected to external supply and ground can drastically de,grade when gate tunneling currents become significant.

Denna post skapades 2006-09-12. Senast ändrad 2016-09-14.
CPL Pubid: 2304


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Institutioner (Chalmers)

Institutionen för datorteknik, Integrerade elektroniksystem (2002-2004)


Information Technology

Chalmers infrastruktur

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