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A Power Cut-Off Technique for Gate Leakage Suppression

Mindaugas Drazdziulis (Institutionen för datorteknik, Integrerade elektroniksystem) ; Per Larsson-Edefors (Institutionen för datorteknik, Integrerade elektroniksystem) ; Daniel Eckerbert (Institutionen för datorteknik, Integrerade elektroniksystem) ; Henrik Eriksson (Institutionen för datorteknik, Integrerade elektroniksystem)
European Solid-State Circuits Conference (ESSCIRC) p. 171-174. (2004)
[Konferensbidrag, refereegranskat]

Gate leakage power dissipation is predicted to overtake subthreshold leakage power within the next few years thus adding further problems for designers trying to meet a strict power budget. In this paper a power cut-off technique is proposed, which in steep mode suppresses not only subthreshold leakage but also gate leakage. The proposed technique displays a combination of low total leakage power and short wake-up time.

Denna post skapades 2006-09-12. Senast ändrad 2016-09-14.
CPL Pubid: 2301


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Institutioner (Chalmers)

Institutionen för datorteknik, Integrerade elektroniksystem (2002-2004)


Information Technology

Chalmers infrastruktur

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