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An Efficient Twin-Precision Multiplier

Magnus Själander (Institutionen för datorteknik, Integrerade elektroniksystem) ; Henrik Eriksson (Institutionen för datorteknik, Integrerade elektroniksystem) ; Per Larsson-Edefors (Institutionen för datorteknik, Integrerade elektroniksystem)
International Conference on Computer Design (ICCD) p. 30-33. (2004)
[Konferensbidrag, refereegranskat]

We present a twin-precision multiplier that in normal operation mode efficiently performs N-b multiplications. For applications where the demand on precision is relaxed, the multiplier can perform N/2-b multiplications while expending only a fraction of the energy of a conventional N-b multiplier. For applications with high demands on throughput, the multiplier is capable of performing two independent N/2-b multiplications in parallel. A comparison between two signed 16-b multipliers, where both perform single 8-b multiplications, shows that the twin-precision multiplier has 72% lower power dissipation and 15% higher speed than the conventional one, while only requiring 8% more transistors.

Denna post skapades 2006-09-12. Senast ändrad 2016-09-14.
CPL Pubid: 2299


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Institutioner (Chalmers)

Institutionen för datorteknik, Integrerade elektroniksystem (2002-2004)


Information Technology

Chalmers infrastruktur

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