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Static Power Reduction and Estimation in CMOS Circuits Considering Emerging Leakage Mechanisms

Mindaugas Drazdziulis (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
Göteborg : Chalmers University of Technology, 2006. ISBN: 91-7291-854-3.- 22 s.
[Doktorsavhandling]

Due to semiconductor technology advancements, the static power dissipation caused by leakage currents in CMOS circuits is growing at a much faster rate than dynamic power; the dominant power component. As a result, controlling and limiting static power becomes as crucial as controlling dynamic power. Out of a number of introduced circuit techniques addressing the leakage issue, power gating shows the most promising results, achieving 100x leakage reduction. Several power-gating techniques have been proposed to date, however, no single one is ideal for all design scenarios. In order to minimize power and maximize performance, selecting the most appropriate power-gating technique for a given design scenario is of paramount importance. This thesis gives guidelines on how to choose the appropriate power-gating technique, depending on design parameters such as performance, power, area, and logic circuit behavior. When large logic blocks are idle for long periods of time and do not need to be activated quickly, power gating employing power switch overdrive should be used. The total power in sleep mode is often minimized when the overdrive voltage is at the maximum level allowed by the semiconductor technology. To deal with the issue of process parameter variations, when generating maximum overdrive voltages, a new generator is proposed. Circuit-level remedies to emerging and harmful leakage mechanisms---most notably gate leakage---are also discussed. Existing power-gating techniques are re-evaluated and compared, with an emphasis on total (subthreshold and gate) leakage power. Subsequently, a new power-gating technique for gate-leakage suppression is proposed. Finally, an approach to accurately capture and characterize emerging leakage mechanisms in SRAM arrays for accurate high-level modeling is proposed.

Nyckelord: VLSI, CMOS, subthreshold, power gating, gate leakage, wake-up time



Denna post skapades 2006-10-03. Senast ändrad 2013-09-25.
CPL Pubid: 22645