CPL - Chalmers Publication Library
| Utbildning | Forskning | Styrkeområden | Om Chalmers | In English In English Ej inloggad.

Table-Based Total Power Consumption Estimation of Memory Arrays for Architects

Minh Quang Do (Institutionen för datorteknik, Embedded and Networked Processors) ; Per Larsson-Edefors (Institutionen för datorteknik, Integrerade elektroniksystem) ; Lars Bengtsson (Institutionen för datorteknik, Embedded and Networked Processors)
Lecture Notes in Computer Science (LNCS) , Springer Verlag Vol. 3254 (2004), 1, p. 869-878.
[Konferensbidrag, refereegranskat]

In this paper, we propose the White-box Table-based Total Power Consumption (WTTPC) estimation approach that offers both rapid and accurate architecture-level power estimation models for some processor components with regular structures, such as SRAM arrays, based on WTTPC-tables of power values. A comparison of power estimates obtained from the proposed approach against circuit-level HSPICE power values for a 64-b conventional 6T-SRAM memory array implemented in a commercial 0.13-um CMOS technology process shows a 98% accuracy of the WTTPC approach.



Denna post skapades 2006-09-19. Senast ändrad 2016-09-14.
CPL Pubid: 2255

 

Läs direkt!


Länk till annan sajt (kan kräva inloggning)


Institutioner (Chalmers)

Institutionen för datorteknik, Embedded and Networked Processors (2002-2004)
Institutionen för datorteknik, Integrerade elektroniksystem (2002-2004)

Ämnesområden

Information Technology

Chalmers infrastruktur

Relaterade publikationer

Denna publikation ingår i:


Accurate Leakage-Conscious Architecture-Level Power Estimation for SRAM-based Memory Structures