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High-speed Binary Signed-Digit RNS adder with posibit and negabit encoding

S. Timarchi ; M. Saremi ; M. Fazlali ; Georgi N. Gaydadjiev (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration, VLSI-SoC 2013; Istanbul; Turkey; 7 October 2013 through 9 October 2013 (2324-8432). p. 58-59. (2013)
[Konferensbidrag, refereegranskat]

Binary Signed-Digit Residue Number System (BSD-RNS) has been proposed in the literatures as an appropriate number system to perform the arithmetic operations in parallel. BSD-RNS addition is the basic operation and improving its performance results in efficient VLSI arithmetic circuits. Here, we present a new architecture for carry-free BSD-RNS addition utilizing a recently proposed posibit and negabit BSD representation. Compared to 2's complement BSD-RNS adder, the proposed architecture has 21% less delay. Besides, for a same delay (0.6ns), we obtain 48% less area and 28% less power than the most efficient existing BSD-RNS adder.

Nyckelord: Binary Signed Digit , Carry-Free Addition , Residue Number System



Denna post skapades 2015-05-04. Senast ändrad 2016-06-30.
CPL Pubid: 216336

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Beräkningsmatematik

Chalmers infrastruktur