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Circuit level, static power, and logic level power analyses

Salar Alipour (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Babak Hidaji (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Amir Sabbagh Pour
2010 IEEE International Conference on Electro/Information Technology, EIT2010, Normal, IL, United States, 20-22 May 2010 (2154-0357). (2010)
[Konferensbidrag, refereegranskat]

Analyzing power consumption is a major factor in CMOS electronic design procedure. Power estimation approaches are more complicated than area and delay estimation since they depend on several factors such as signal transitions, clock frequency, CMOS technology, circuit's design and etc. This article describes different components of power dissipation in CMOS circuits such as Short Circuit, Static and Dynamic power, as a background to ease the way of further discussion on estimation methods. The major concept of the paper presents some power estimation methods at circuit and logic level and also static power analyses. Two main logic level estimation methods, Simulation-Based and probabilistic techniques are briefly described. The paper is finalized by comparison of the result of different power estimation method on an ALU circuit.



Denna post skapades 2015-05-04. Senast ändrad 2016-07-07.
CPL Pubid: 216319

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)
Institutionen för data- och informationsteknik (GU) (GU)

Ämnesområden

Data- och informationsvetenskap

Chalmers infrastruktur