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Design trade-offs in energy efficient NoC architectures

A. Psathakis ; Vasileios Papaefstathiou (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; M.G.H. Katevenis ; D.N. Pnevmatikatos
8th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2014; Ferrara; Italy; 17 September 2014 through 19 September 2014 p. 186-187. (2014)
[Konferensbidrag, refereegranskat]

This paper studies design trade-offs in energy efficient Networks-on-Chip by evaluating every network architecture that derives when we apply all possible variations of design-configuration parameters on a baseline 2D mesh. Network separation (P), concentration (C), express channels (X), flit widths (W), and virtual channels (V). Our comperative analysis selects the network architecture configuration that gives the best energy delay product (EDP) while allowing a maximum area margin of 15% over the most energy efficient configuration of the baseline.

Denna post skapades 2015-03-03.
CPL Pubid: 213346


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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)



Chalmers infrastruktur