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MIDAS: Model for IP-inclusive DFM assessment of system manufacturability

Kasyab P. Subramaniyan (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Per Larsson-Edefors (Institutionen för data- och informationsteknik, Datorteknik (Chalmers))
5th European Workshop on CMOS Variability, VARI 2014. Palma de Mallorca, SPAIN, SEP 29-OCT 01, 2014 p. Art. no. 6957079. (2014)
[Konferensbidrag, refereegranskat]

Complex system implementations combined with the latest technology nodes allow us to implement hardware for versatile applications. The ever increasing demand for quick time-to-market has led to the widespread use of Intellectual Property (IP) in ASIC design methodologies. These developments, in addition to manufacturing limitations, make early prediction of manufacturability for complete systems challenging. We present MIDAS: a scalable, IP-inclusive model to predict system manufacturability. Results from applying MIDAS to an embedded processor system reveals that several useful insights can be gained towards realizing yield budgets for complex systems allowing quicker co-optimization of all implementation goals.

Nyckelord: ASIC , DFM Metrics , IP , Manufacturability

Denna post skapades 2015-01-02. Senast ändrad 2016-09-14.
CPL Pubid: 209306


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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)


Data- och informationsvetenskap

Chalmers infrastruktur