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FPGA-based design using the FASTER toolchain: The case of STM spear development board

F. Spada ; A. Scolari ; G.C. Durelli ; R. Cattaneo ; M.D. Santambrogio ; D. Sciuto ; D.N. Pnevmatikatos ; Georgi N. Gaydadjiev (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; O. Pell ; A. Brokalakis ; W. Luk ; D. Stroobandt ; D. Pau
Proceedings - 2014 IEEE International Symposium on Parallel and Distributed Processing with Applications, ISPA 2014 p. 134-141. (2014)
[Konferensbidrag, refereegranskat]

Even though FPGAs are becoming more and more popular as they are used in many different scenarios like communications and HPC, the steep learning curve needed to work with this technology is still the major limiting factor to their full success. Many works proposed to mitigate this problem by creating a companion of tools to support the designer during the development phase for this technology. The EU FASTER Project aims at realizing an integrated toolchain that assists the designer in the steps of the design flow that are necessary to port a given application onto an FPGA device. The novelty of the framework relies in the fact that the partial dynamic reconfiguration, which FPGA devices can exploit, is seen as a first class citizen throughout the whole design flow. This work reports a case study in which the FASTER toolchain has been used to port a raytracer application onto the STM Spear prototyping embedded platform. The paper discusses the steps done for the realization of the prototype and the results obtained on the target device. It finally reports some improvements that can be exploited to improve the performance of the hardware implementation that has been realized.

Nyckelord: partial reconfiguration


Article number 6924439



Denna post skapades 2014-12-04. Senast ändrad 2016-01-07.
CPL Pubid: 207426

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Data- och informationsvetenskap

Chalmers infrastruktur