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A Functional Language-Based Approach to Low-Level Hardware Design

Emil Axelsson (Institutionen för data- och informationsteknik, Datavetenskap (Chalmers))
Göteborg : Chalmers University of Technology, 2006. - 81 s.

The semiconductor industry is facing increasing problems with designing complex circuits with tight constraints on area, performance and power consumption. Worse still, these circuits must be designed and verified very quickly. The existing design tools have great problems with handling the complexity of the designs, and time consuming manual intervention is often needed in order to reach a satisfactory result. One factor in this increasing complexity is the fact that routing wires dominate logical gates in today's high-performance circuits when non-functional properties such as signal delay and power consumption are considered. In conventional design methods, information about routing wires is not included until the later design stages, so that bad choices early on are not discovered until after the time consuming physical design stage. In order to overcome this problem, we need design methods which take wire effects into account right from the start. This requires better abstraction techniques that faithfully model the lower-level implications, even when working at a high level of abstraction. We propose a system called {\em Wired}, which allows layout- and wire-aware design at higher abstraction level than any similar approach that we know of. Wired is based on a simple relational programming language, which in turn, is embedded in the functional programming language Haskell. This gives a very powerful and flexible system for describing low-level aware circuit generators. Combining Wired with Lava -- a similar system, but with less support for the analysis of low-level properties -- gives a powerful design flow in which a design can start off as a relatively high-level functional Lava description, and then be gradually refined into a low-level Wired description. We demonstrate through case studies of parallel prefix networks that the link between the high-level and the low-level description can be made very clear, allowing changes to be propagated up and down through the abstractions. The system supports the analysis of non-functional properties that depend on wire effects. In particular, a bidirectional analysis that calculates RC-delays has been implemented, exploiting the fact that Wired is a relational programming language. This, combined with succinct circuit descriptions, enables rapid design exploration, in which candidate designs are compared for performance.

Nyckelord: electronic design automation (EDA), interconnect, non-functional properties, wire-aware circuit generators, design exploration, functional programming

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Denna post skapades 2006-08-25. Senast ändrad 2015-11-17.
CPL Pubid: 19989