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Techniques to Improve Performance in Requester-Wins Hardware Transactional Memory

A. Armejach ; Ruben Titos Gil (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Anurag Negi (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; O .S. Unsal ; A. Cristal
ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION (1544-3566). Vol. 10 (2013), 4, p. articlenr, 42.
[Artikel, refereegranskad vetenskaplig]

The simplicity of requester-wins Hardware Transactional Memory (HTM) makes it easy to incorporate in existing chip multiprocessors. Hence, such systems are expected to be widely available in the near future. Unfortunately, these implementations are prone to suffer severe performance degradation due to transient and persistent livelock conditions. This article shows that existing techniques are unable to mitigate this degradation effectively. It then proposes and evaluates four novel techniques-two software-based that employ information provided by the hardware and two that require simple core-local hardware additions-which have the potential to boost the performance of requester-wins HTM designs substantially.

Nyckelord: Contention management, hardware transactional memory, requester-wins conflict resolution



Denna post skapades 2014-03-13.
CPL Pubid: 194884

 

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Institutioner (Chalmers)

Institutionen för data- och informationsteknik, Datorteknik (Chalmers)

Ämnesområden

Datavetenskap (datalogi)

Chalmers infrastruktur

 


Projekt

Denna publikation är ett resultat av följande projekt:


High Performance and Embedded Architecture and Compilation (HIPEAC) (EC/FP7/287759)