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Portable, scalable, per-core power estimation for intelligent resource management

Bhavishya Goel (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Sally A McKee (Institutionen för data- och informationsteknik, Datorteknik (Chalmers)) ; Roberto Gioiosa ; Karan Singh ; Major Bhadauria ; Marco Cesati
International Green Computing Conference, 2010, Chicago, USA p. 135-146. (2010)
[Konferensbidrag, refereegranskat]

Performance, power, and temperature are now all first-order design constraints. Balancing power efficiency, thermal constraints, and performance requires some means to convey data about real-time power consumption and temperature to intelligent resource managers. Resource managers can use this information to meet performance goals, maintain power budgets, and obey thermal constraints. Unfortunately, obtaining the required machine introspection is challenging. Most current chips provide no support for per-core power monitoring, and when support exists, it is not exposed to software. We present a methodology for deriving per-core power models using sampled performance counter values and temperature sensor readings. We develop application-independent models for four different (four- to eight-core) platforms, validate their accuracy, and show how they can be used to guide scheduling decisions in power-aware resource managers. Model overhead is negligible, and estimations exhibit 1.1%-5.2% per-suite median error on the NAS, SPEC OMP, and SPEC 2006 benchmarks (and 1.2%-4.4% overall).

Nyckelord: application-independent models, chip multiprocessor systems, intelligent resource management, per-core power estimation, power efficiency

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Denna post skapades 2014-02-18. Senast ändrad 2016-03-22.
CPL Pubid: 193921


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