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Improved GaN-on-SiC transistor thermal resistance by systematic nucleation layer growth optimization

J. Pomeroy ; Niklas Rorsman (Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik) ; J.-T. Chen ; U. Forsberg ; E. Janzen ; M. Kuball
Technical Digest - IEEE Compound Semiconductor Integrated Circuit Symposium, CSIC (2013)
[Konferensbidrag, refereegranskat]

Impressive power densities have been demonstrated for GaN-on-SiC based high-power high-frequency transistors, although further gains can be achieved by further minimizing the device thermal resistance. A significant 10-30% contribution to the total device thermal resistance originates from the high defect density AlN nucleation layer at the GaN/SiC interface. This thermal resistance contribution was successfully reduced by performing systematic growth optimization, investigating growth parameters including: Substrate pretreatment temperature, growth temperature and deposition time. Interfacial thermal resistance, characterized by time resolved Raman thermography measurements AlGaN/GaN HEMT structures, were minimized by using a substrate pretreatment and growth temperature of 1200 °C. Reducing the AlN thickness from 105 nm (3.3×10-8 W/m2K) to 35 nm (3.3×10-8 W/m2K), led to a ~2.5× interfacial thermal resistance reduction and the lowest value reported for a standard AlGaN/GaN HEMT structure.

Denna post skapades 2014-02-18. Senast ändrad 2015-07-28.
CPL Pubid: 193908


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Institutioner (Chalmers)

Institutionen för mikroteknologi och nanovetenskap, Mikrovågselektronik


Elektroteknik och elektronik

Chalmers infrastruktur